Frontier of On-device AI Semiconductors
for Everyone, Everywhere
We are looking for a talented engineer to join us in developing the DDR memory subsystem, a key component of our next-generation SoCs. In this role, you will be involved in various stages of memory subsystem development, including IP integration and verification, system bring-up, and performance/power optimization.
We expect you to leverage your experience and expertise to become a core member of our team and play a critical role in leading projects to success.
Responsibilities
□ 3rd-Party DDR IP Integration and SoC Interface Verification
- Integrate external DDR Controller and PHY IPs (e.g., Synopsys, Cadence) into the SoC RTL, and design and verify related wrapper and interface logic.
- Verify protocol specifications and performance requirements between the SoC's internal interconnect (AXI/CHI, NoC, etc.) and the memory controller.
- Define SoC-level Timing Constraints and collaborate with the STA (Static Timing Analysis) and Physical Design teams on floorplanning.
- Participate in defining the PKG Ball map and Die Bump map to optimize high-speed/low-speed DDR signal placement and lead I/O planning with a focus on SI/PI (Signal/Power Integrity).
- Analyze memory bandwidth and latency based on system workloads and resolve bottlenecks.
- Verify and optimize the low-power functions of DRAM (Self-refresh, Deep Power-Down, etc.) and the SoC's DVFS (Dynamic Voltage and Frequency Scaling) operation.
□ Pre-Silicon Verification
- Perform functional and performance verification regressions of the DDR subsystem in a SystemVerilog/UVM-based testbench environment.
- Develop corner-case and stress test scenarios based on JEDEC standards (LPDDR5/5X, DDR5, etc.).
- Perform timing verification and gate-level verification through post-layout, back-annotated simulations.
□ Firmware Integration and DDR Initialization/Training
- Collaborate with the boot firmware and driver teams to port and optimize the DDR initialization sequence and training algorithms (e.g., CA/DQ training).
- Analyze firmware packages provided by IP vendors and customize and debug them for the SoC environment.
□ Post-Silicon Validation & System Bring-up
- Lead the DDR interface bring-up and stability verification on actual boards with silicon.
- Measure DDR signals and debug at the protocol level using a high-speed oscilloscope, logic analyzer, and protocol analyzer.
- Analyze and optimize operating margins through Shmoo tests under various PVT (Process, Voltage, Temperature) conditions.
- Measure and analyze SI/PI (Signal/Power Integrity) (e.g., Eye-diagram, Jitter, Vref tuning, ODT calibration).
□ Mass Production Test and Yield Analysis
- Develop test patterns and programs to verify key functions and electrical characteristics of the DDR interface in a mass-production ATE (Automated Test Equipment) test environment, and collaborate with test engineers to debug issues.
- Verify the stability and performance of the DDR subsystem with various traffic patterns and stress conditions in an SLT (System Level Test) environment and establish criteria for pass/fail.
- Analyze DDR-related failures in modules or final products (boards) with mass-produced chips, and identify the root cause of yield degradation based on test data to improve the design and test program.
- Lead in-depth analysis of field failures received through RMA (Return Merchandise Authorization) to pinpoint the root cause and provide feedback for next-generation products.
□ Internal/External Collaboration
- Jointly analyze and resolve compatibility issues with DRAM vendors (Samsung, SK Hynix, Micron, etc.).
- Maintain regular communication with IP vendors to track bugs, find solutions, and coordinate IP release schedules.
Qualifications
□ Bachelor's degree or higher in Electrical/Computer Engineering or a related field.
□ Deep understanding of JEDEC DDR/LPDDR standards (DDR4/5, LPDDR4/5, etc.).
□ Proficiency in scripting languages such as Python, Perl, and Tcl.
Preferred Qualifications
□ Master's or Ph.D. degree.
□ N+ years of experience with DDR/LPDDR controller or PHY development.
□ Hands-on experience with DDR subsystem bring-up and debugging on actual silicon.
□ Proficiency with lab equipment such as high-speed oscilloscopes and logic analyzers.
□ Experience collaborating with major IP vendors like Synopsys, Cadence, and Rambus.
□ Experience building SystemVerilog/UVM-based RTL verification environments and writing test scenarios.
□ Experience using SI/PI (Signal/Power Integrity) analysis tools (e.g., HSPICE, ADS).
□ Experience analyzing and optimizing DDR training algorithms at the firmware/driver level.
□ Experience with the entire SoC project lifecycle from tape-out to mass production.
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
Frontier of On-device AI Semiconductors
for Everyone, Everywhere
We are looking for a talented engineer to join us in developing the DDR memory subsystem, a key component of our next-generation SoCs. In this role, you will be involved in various stages of memory subsystem development, including IP integration and verification, system bring-up, and performance/power optimization.
We expect you to leverage your experience and expertise to become a core member of our team and play a critical role in leading projects to success.
Responsibilities
□ 3rd-Party DDR IP Integration and SoC Interface Verification
- Integrate external DDR Controller and PHY IPs (e.g., Synopsys, Cadence) into the SoC RTL, and design and verify related wrapper and interface logic.
- Verify protocol specifications and performance requirements between the SoC's internal interconnect (AXI/CHI, NoC, etc.) and the memory controller.
- Define SoC-level Timing Constraints and collaborate with the STA (Static Timing Analysis) and Physical Design teams on floorplanning.
- Participate in defining the PKG Ball map and Die Bump map to optimize high-speed/low-speed DDR signal placement and lead I/O planning with a focus on SI/PI (Signal/Power Integrity).
- Analyze memory bandwidth and latency based on system workloads and resolve bottlenecks.
- Verify and optimize the low-power functions of DRAM (Self-refresh, Deep Power-Down, etc.) and the SoC's DVFS (Dynamic Voltage and Frequency Scaling) operation.
□ Pre-Silicon Verification
- Perform functional and performance verification regressions of the DDR subsystem in a SystemVerilog/UVM-based testbench environment.
- Develop corner-case and stress test scenarios based on JEDEC standards (LPDDR5/5X, DDR5, etc.).
- Perform timing verification and gate-level verification through post-layout, back-annotated simulations.
□ Firmware Integration and DDR Initialization/Training
- Collaborate with the boot firmware and driver teams to port and optimize the DDR initialization sequence and training algorithms (e.g., CA/DQ training).
- Analyze firmware packages provided by IP vendors and customize and debug them for the SoC environment.
□ Post-Silicon Validation & System Bring-up
- Lead the DDR interface bring-up and stability verification on actual boards with silicon.
- Measure DDR signals and debug at the protocol level using a high-speed oscilloscope, logic analyzer, and protocol analyzer.
- Analyze and optimize operating margins through Shmoo tests under various PVT (Process, Voltage, Temperature) conditions.
- Measure and analyze SI/PI (Signal/Power Integrity) (e.g., Eye-diagram, Jitter, Vref tuning, ODT calibration).
□ Mass Production Test and Yield Analysis
- Develop test patterns and programs to verify key functions and electrical characteristics of the DDR interface in a mass-production ATE (Automated Test Equipment) test environment, and collaborate with test engineers to debug issues.
- Verify the stability and performance of the DDR subsystem with various traffic patterns and stress conditions in an SLT (System Level Test) environment and establish criteria for pass/fail.
- Analyze DDR-related failures in modules or final products (boards) with mass-produced chips, and identify the root cause of yield degradation based on test data to improve the design and test program.
- Lead in-depth analysis of field failures received through RMA (Return Merchandise Authorization) to pinpoint the root cause and provide feedback for next-generation products.
□ Internal/External Collaboration
- Jointly analyze and resolve compatibility issues with DRAM vendors (Samsung, SK Hynix, Micron, etc.).
- Maintain regular communication with IP vendors to track bugs, find solutions, and coordinate IP release schedules.
Qualifications
□ Bachelor's degree or higher in Electrical/Computer Engineering or a related field.
□ Deep understanding of JEDEC DDR/LPDDR standards (DDR4/5, LPDDR4/5, etc.).
□ Proficiency in scripting languages such as Python, Perl, and Tcl.
Preferred Qualifications
□ Master's or Ph.D. degree.
□ N+ years of experience with DDR/LPDDR controller or PHY development.
□ Hands-on experience with DDR subsystem bring-up and debugging on actual silicon.
□ Proficiency with lab equipment such as high-speed oscilloscopes and logic analyzers.
□ Experience collaborating with major IP vendors like Synopsys, Cadence, and Rambus.
□ Experience building SystemVerilog/UVM-based RTL verification environments and writing test scenarios.
□ Experience using SI/PI (Signal/Power Integrity) analysis tools (e.g., HSPICE, ADS).
□ Experience analyzing and optimizing DDR training algorithms at the firmware/driver level.
□ Experience with the entire SoC project lifecycle from tape-out to mass production.
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원