□ Perform full physical design implementation for DeepX’s NPU chips
□ Synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing
□ Timing closure and optimization of power, area, and performance (PPA)
□ Post-layout verification and debug: DRC, LVS, Crosstalk, EMIR, etc.
□ Automate physical design flows using scripting (Tcl, Python, etc.)
□ Bachelor’s degree or higher in Electrical/Electronic Engineering or related field
□ Experience or project work in ASIC physical design
□ Hands-on experience with major EDA tools (e.g., Synopsys ICC2, Cadence Innovus)
□ Understanding of RTL to GDSII design flow
□ Proficiency in scripting languages (Tcl, Perl, Python, etc.)
□ Experience with advanced process nodes
□ Knowledge of low-power design techniques (power gating, multi-Vt, clock gating, etc.)
□ Experience with physical-aware synthesis and timing-driven place & route
□ In-depth experience with static timing analysis (STA)
□ Comfortable working in a startup environment with a problem-solving mindset
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
□ Full-time (3-month probationary period with 100% compensation)
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
□ Perform full physical design implementation for DeepX’s NPU chips
□ Synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing
□ Timing closure and optimization of power, area, and performance (PPA)
□ Post-layout verification and debug: DRC, LVS, Crosstalk, EMIR, etc.
□ Automate physical design flows using scripting (Tcl, Python, etc.)
□ Bachelor’s degree or higher in Electrical/Electronic Engineering or related field
□ Experience or project work in ASIC physical design
□ Hands-on experience with major EDA tools (e.g., Synopsys ICC2, Cadence Innovus)
□ Understanding of RTL to GDSII design flow
□ Proficiency in scripting languages (Tcl, Perl, Python, etc.)
□ Experience with advanced process nodes
□ Knowledge of low-power design techniques (power gating, multi-Vt, clock gating, etc.)
□ Experience with physical-aware synthesis and timing-driven place & route
□ In-depth experience with static timing analysis (STA)
□ Comfortable working in a startup environment with a problem-solving mindset
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
□ Full-time (3-month probationary period with 100% compensation)
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원