Frontier of On-device AI Semiconductors
for Everyone, Everywhere
About DeepX Co., Ltd.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
Role Overview
As a CPU Integration Engineer at DEEPX, you will play a pivotal role in the development of our next-generation AI Inference Solutions. You will be responsible for integrating high-performance CPU subsystems into our NPU-centric SoCs, ensuring seamless communication between the processing cores, memory hierarchy, and our proprietary AI accelerators. This role sits at the intersection of architecture design and physical implementation, requiring a deep understanding of bus protocols and system-level performance.
Responsibilities
□ Subsystem Integration: Integrate ARM or RISC-V based CPU IP into AI SoC platforms, focusing on top-level connectivity and hierarchy.
□ Bus & Interconnect Design: Design and configure high-speed on-chip interconnects (NoC/NIC) using protocols such as AMBA (AXI, ACE, CHI) to ensure low-latency data paths.
□ Memory Hierarchy Management: Define and optimize the integration of L2/L3 caches, Snoop Control Units (SCU), and memory controllers.
□ Architecture Validation: Perform RTL-level integration checks, linting, and CDC (Clock Domain Crossing) analysis to ensure design integrity.
□ Performance Tuning: Collaborate with the Architecture team to analyze and resolve system bottlenecks related to CPU-to-NPU communication.
□ Cross-functional Collaboration: Work closely with Front-end/Back-end teams and Software/Firmware teams to define boot sequences and power management schemes.
Qualifications
□ Experience in Cortex-A series and multi-cluster integration required.
□ Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
□ Experience: 5+ years of experience in SoC integration or RTL design.
□ Technical Skills: * Proficiency in Hardware Description Languages (Verilog, SystemVerilog).
- Strong understanding of AMBA protocols (AXI4, ACE, CHI).
- Experience with CPU IPs (ARM Cortex-A/R/M series or RISC-V).
- Familiarity with SoC design flows and EDA tools (e.g., Synopsys Platform Architect, Cadence Genus).
Preferred Qualifications
□ Experience of FPGA Implementation
□ NoC Expertise: Hands-on experience with Network-on-Chip (NoC) IP (e.g., Arteris, ARM CoreLink).
□ Low Power Design: Knowledge of UPF/CPF based power intent and multi-voltage domain integration.
□ Security Integration: Experience integrating hardware security modules (TrustZone, Root of Trust).
□ Advanced Nodes: Experience in advanced process nodes (5nm, 4nm, or below).
□ Problem Solving: A proactive mindset with the ability to navigate the complexities of cutting-edge AI hardware.
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
Frontier of On-device AI Semiconductors
for Everyone, Everywhere
About DeepX Co., Ltd.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
Role Overview
As a CPU Integration Engineer at DEEPX, you will play a pivotal role in the development of our next-generation AI Inference Solutions. You will be responsible for integrating high-performance CPU subsystems into our NPU-centric SoCs, ensuring seamless communication between the processing cores, memory hierarchy, and our proprietary AI accelerators. This role sits at the intersection of architecture design and physical implementation, requiring a deep understanding of bus protocols and system-level performance.
Responsibilities
□ Subsystem Integration: Integrate ARM or RISC-V based CPU IP into AI SoC platforms, focusing on top-level connectivity and hierarchy.
□ Bus & Interconnect Design: Design and configure high-speed on-chip interconnects (NoC/NIC) using protocols such as AMBA (AXI, ACE, CHI) to ensure low-latency data paths.
□ Memory Hierarchy Management: Define and optimize the integration of L2/L3 caches, Snoop Control Units (SCU), and memory controllers.
□ Architecture Validation: Perform RTL-level integration checks, linting, and CDC (Clock Domain Crossing) analysis to ensure design integrity.
□ Performance Tuning: Collaborate with the Architecture team to analyze and resolve system bottlenecks related to CPU-to-NPU communication.
□ Cross-functional Collaboration: Work closely with Front-end/Back-end teams and Software/Firmware teams to define boot sequences and power management schemes.
Qualifications
□ Experience in Cortex-A series and multi-cluster integration required.
□ Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
□ Experience: 5+ years of experience in SoC integration or RTL design.
□ Technical Skills: * Proficiency in Hardware Description Languages (Verilog, SystemVerilog).
- Strong understanding of AMBA protocols (AXI4, ACE, CHI).
- Experience with CPU IPs (ARM Cortex-A/R/M series or RISC-V).
- Familiarity with SoC design flows and EDA tools (e.g., Synopsys Platform Architect, Cadence Genus).
Preferred Qualifications
□ Experience of FPGA Implementation
□ NoC Expertise: Hands-on experience with Network-on-Chip (NoC) IP (e.g., Arteris, ARM CoreLink).
□ Low Power Design: Knowledge of UPF/CPF based power intent and multi-voltage domain integration.
□ Security Integration: Experience integrating hardware security modules (TrustZone, Root of Trust).
□ Advanced Nodes: Experience in advanced process nodes (5nm, 4nm, or below).
□ Problem Solving: A proactive mindset with the ability to navigate the complexities of cutting-edge AI hardware.
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원