Frontier of On-device AI Semiconductors
for Everyone, Everywhere
DEEPX is a leading global tech startup at the forefront of the On-Device AI semiconductor market, built on a dual success formula: Arm’s "ultra-low power technology" and a Qualcomm-style "core patent-based IP portfolio." Having conducted performance tests with over 300 global companies, we are recognized for delivering world-class power efficiency and cost-effectiveness, supported by a formidable portfolio of over 400 AI semiconductor patents worldwide. On the strength of these R&D and commercialization achievements, DEEPX successfully secured large-scale investment in 2024. We are now leading the commercialization of AI across diverse sectors—including smart devices, smart mobility, and industrial automation—within the On-Device AI market, which is projected to reach $10.6 billion by 2030.
Responsibilities
□ RTL-based hardware IP design (focused on AI hardware processor development)
Qualifications
□ Verilog RTL design in a Linux environment
□ Simulation model and testbench development
□ RTL simulation and verification
□ Ability to design RTL IP based on C models and perform IP verification
□ Programming languages: Python/Perl, C/C++
Preferred Qualifications
□ Experience in ARM-based SoC design
□ Experience in designing ARM (AHB, AXI) SoC platforms and peripheral IP
□ Experience with FPGA and ASIC design using high-speed interface IPs (PCIe, USB, SATA, DDR/LPDDR, etc.)
□ Familiarity with EDA tools such as VCS/NC Sim, Verdi, Design Compiler, PrimeTime, Formality, SpyGlass, etc.
□ Experience with design constraint (DC) setup
□ Experience in RTL design related to Clock Domain Crossing (CDC)
□ Experience with ASIC mass production
□ Experience with FPGA prototyping
□ Knowledge of artificial neural networks and deep learning
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
Frontier of On-device AI Semiconductors
for Everyone, Everywhere
DEEPX is a leading global tech startup at the forefront of the On-Device AI semiconductor market, built on a dual success formula: Arm’s "ultra-low power technology" and a Qualcomm-style "core patent-based IP portfolio." Having conducted performance tests with over 300 global companies, we are recognized for delivering world-class power efficiency and cost-effectiveness, supported by a formidable portfolio of over 400 AI semiconductor patents worldwide. On the strength of these R&D and commercialization achievements, DEEPX successfully secured large-scale investment in 2024. We are now leading the commercialization of AI across diverse sectors—including smart devices, smart mobility, and industrial automation—within the On-Device AI market, which is projected to reach $10.6 billion by 2030.
Responsibilities
□ RTL-based hardware IP design (focused on AI hardware processor development)
Qualifications
□ Verilog RTL design in a Linux environment
□ Simulation model and testbench development
□ RTL simulation and verification
□ Ability to design RTL IP based on C models and perform IP verification
□ Programming languages: Python/Perl, C/C++
Preferred Qualifications
□ Experience in ARM-based SoC design
□ Experience in designing ARM (AHB, AXI) SoC platforms and peripheral IP
□ Experience with FPGA and ASIC design using high-speed interface IPs (PCIe, USB, SATA, DDR/LPDDR, etc.)
□ Familiarity with EDA tools such as VCS/NC Sim, Verdi, Design Compiler, PrimeTime, Formality, SpyGlass, etc.
□ Experience with design constraint (DC) setup
□ Experience in RTL design related to Clock Domain Crossing (CDC)
□ Experience with ASIC mass production
□ Experience with FPGA prototyping
□ Knowledge of artificial neural networks and deep learning
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원