Frontier of On-device AI Semiconductors
for Everyone, Everywhere
Role Overview
□ Develop key components and core technologies that enable various (based-on-SOTA) AI models to run efficiently on NPUs.
□ Research NPU hardware architecture optimized for low power consumption and high performance.
□ Design data workloads that maximize energy efficiency of conventional NPUs.
□ Continuously evaluate and ensure alignment between user requirements and NPU specifications.
□ Conduct ongoing research and development on NPU hardware bottlenecks and breaking points.
Responsibilities
□ Explore, discuss, and determine NPU architectures that meet required specifications.
□ Collaborate with internal teams or customers to develop profiling tools tailored to specific needs.
□ Predict hardware-friendly performance quickly and accurately for neural networks using C++ or SystemC.
□ Work closely with deep learning, RTL, and compiler teams to design efficient engineering methodologies and NPU architectures.
□ Propose advanced NPU architectures based on new network analysis and consideration of system components.
Qualifications
□ Solid understanding of chip architecture, including CPU, memory, and bus systems
□ Proficiency in architecture-level modeling using SystemC
□ Experience in PPA (Power, Performance, Area) estimation
□ Strong ability to handle and analyze large-scale data
□ Effective communicator who engages actively with cross-functional teams
Preferred Qualifications
□ Over 10 years of experience (including graduate studies) in the field of chip architecture
□ Hands-on experience with various neural network frameworks and a strong interest in AI technologies
□ Strong organizational skills with the ability to manage tasks systematically
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
Frontier of On-device AI Semiconductors
for Everyone, Everywhere
Role Overview
□ Develop key components and core technologies that enable various (based-on-SOTA) AI models to run efficiently on NPUs.
□ Research NPU hardware architecture optimized for low power consumption and high performance.
□ Design data workloads that maximize energy efficiency of conventional NPUs.
□ Continuously evaluate and ensure alignment between user requirements and NPU specifications.
□ Conduct ongoing research and development on NPU hardware bottlenecks and breaking points.
Responsibilities
□ Explore, discuss, and determine NPU architectures that meet required specifications.
□ Collaborate with internal teams or customers to develop profiling tools tailored to specific needs.
□ Predict hardware-friendly performance quickly and accurately for neural networks using C++ or SystemC.
□ Work closely with deep learning, RTL, and compiler teams to design efficient engineering methodologies and NPU architectures.
□ Propose advanced NPU architectures based on new network analysis and consideration of system components.
Qualifications
□ Solid understanding of chip architecture, including CPU, memory, and bus systems
□ Proficiency in architecture-level modeling using SystemC
□ Experience in PPA (Power, Performance, Area) estimation
□ Strong ability to handle and analyze large-scale data
□ Effective communicator who engages actively with cross-functional teams
Preferred Qualifications
□ Over 10 years of experience (including graduate studies) in the field of chip architecture
□ Hands-on experience with various neural network frameworks and a strong interest in AI technologies
□ Strong organizational skills with the ability to manage tasks systematically
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원